Embedded dynamic random access memories (eDRAM) are widely used for their improved performances in high-speed applications, such as computing units (CPU).
In eDRAM circuits, local bit lines are connected to eDRAM cells and global bit lines, which are further connected to control circuits. Through the global bit lines and the connecting local bit lines, write operations may be performed to write to eDRAM cells. The local bit lines typically include two lines with often-inversed phases, namely BL and ZBL. The global bit lines also typically include two lines with often-inversed phases, namely GBL and ZGBL.
Preferably, in a write operation of an eDRAM cell, the global bit lines are pre-charged to the desirable voltage levels. After the pre-charge is finished, a word line connected to the eDRAM cell is enabled to start writing into the eDRAM cell. After the write operation, the global bit lines need to be pre-charged again, so that the next write operation may be performed. The two consecutive write operations are referred to as back-to-back write operations. The back-to-back write operations run into a problem when worked under high frequencies: there may not be enough time for global bit lines to be pre-charged because the time allowed for pre-charging is too short. To make it worse, although the pre-charge time may be prolonged by starting the pre-charge earlier, such an action will adversely affect the read operations since read operations prefer the corresponding pre-charges to start late.
FIG. 1 illustrates waveforms obtained from a convention eDRAM circuit. A GBL pre-charge enable signal 20 enables the pre-charge (the rising edge 20). The pre-charge results in the voltage (line 6) of global bit line GBL to rise, and the voltage (line 8) of global bit line ZGBL to drop. However, before global bit line ZGBL can drop to ground level (0V), the rising edge 3 of the word line voltage (line 2) has enabled the writing (at time T). Accordingly, there is not enough time left for the pre-charge to finish. In this case, the GBL pre-charge enable signal 20 is used for enabling the global bit line pre-charges of both read and write operations. Therefore, regardless of whether the subsequent operation is a read or a write operation, the pre-charge time is the same.
The un-finished pre-charge will adversely affect the local bit lines. It is preferred that when local bit lines BL and ZBL go into a charge-sharing stage, the global bit lines are pre-charged fully, for example, the global bit line ZGBL to substantially reach ground voltage, while the global bit line GBL has a voltage substantially reaching the operation voltage VDD. However, inadequate pre-charge time will cause the local bit lines (line 10 indicating the voltage of local bit line BL, and line 12 indicating the voltage of local bit line BLB) to start sharing charges (section 14) before global bit line ZGBL is fully grounded. The signals on the local bit lines BL and BLB will thus be adversely affected.
Accordingly, what is needed in the art is a method for fully pre-charging global bit lines, so that write operations may be improved, while at the same time without causing the degradation in read operations.